1. References
The following papers provide useful background information, for which they are incorporated herein by reference in their entirety, and are selectively referred to in the remainder of this disclosure by their accompanying reference numbers in square brackets (i.e., [3] for the third numbered paper by J. Monteiro and S. Devdas):
[1] D. Belete, A. Razdan, W. Schwarz, R. Raina, C. Hawkins, and J. Morehead. Use of DFT Techniques In Speed Grading a 1 GHz+ Microprocessor. In Proceedings IEEE International Test Conference, pages 1111–1119, 2002.
[2] K.-T. Cheng, S. Devadas, and K. Keutzer. A Partial Enhanced-Scan Approach to Robust Delay-Generation for Sequential Circuits}. In Proceedings IEEE International Test Conference, pages 403–410, 1991.
[3] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy. Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application. In IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, Vol. 17(12), December 1998.
[4] B. Dervisoglu and G. Stong. Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement. In Proceedings IEEE International Test Conference, pages 365–374, 1991.
[5] S. Gerstendorfer and H.-J. Wunderlich. Minimized Power Consumption for Scan-Based BIST. In Proceedings IEEE International Test Conference, pages 77–84, 1999.
[6] M. J. Geuzebroek, J. T. van der Linden, and A. J. van de Goor. Test Point Insertion for Compact Test Sets}. In Proceedings IEEE International Test Conference, pages 292–301, 2000.
[7] P. Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits}. In IEEE Trans. on Computers, Vol. C-30(3), March 1981.
[8] L. H. Goldstein and E. L. Thigpen. SCOAP: Sandia Controllability/Observability Analysis Program. In Proceedings IEEE-ACM Design Automation Conference, pages 190–196, 1980.
[9] W. Mao and M. D. Ciletti. Reducing Correlation to Improve Coverage of Delay Faults in Scan-Path Design}. In IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, Vol. 13(5), May 1994.
[10] I. Pomeranz and S. M. Reddy. On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines. In Proceedings IEEE International Test Conference, pages 923–931, 1999.
[11] J. Savir and R. Berry. At-Speed Test is not Necessarily an AC Test. In Proceedings IEEE International Test Conference, pages 722–728, 1991.
[12] J. Savir and S. Patil. Scan-Based Transition Test. In IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, Vol. 12(8), August 1993.
[13] J. Savir and S. Patil. Broad-Side Delay Test. In Transactions on Computer-Aided Design of Integrated Circuit and System, Vol. 13(8), August 1994.
[14] J. Saxena, K. M. Butler, J. Gatt, R. R, S. P. Kumar, S. Basu, D. J. Campbell, and J. Berech. Scan-Based Transition Fault Testing—Implementation and Low Cost Test Challenges. In Proceedings IEEE International Test Conference, pages 1120–1129, 2002.
[15] G. L. Smith. Model for Delay Faults Based Upon Paths. In Proceedings IEEE International Test Conference, pages 342–349, 1985.
[16] IEEE standard 1149.1-2001. IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEEE standard board, New York, N.Y., 1990.
[17] N. Tamarapalli and J. Rajski. Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. In Proceedings IEEE International Test Conference, pages 649–658, 1996.
[18] J. A. Waicukauski, E. Lindbloom, B. K. Rosen, and V. S. Iyengar. Transition Fault Simulation. In IEEE Design & Test of Computers, pages 32–38, April 1987.
[19] S. Wang and S. K. Gupta. DS-LFSR: A BIST TPG for Low Switching Activity. In IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, Vol. 21(7), July 2002.
2. Related Work
Ascertaining correct operation of digital circuits at desired speed is becoming more important. Conventionally, at-speed testing was typically accomplished with functional test patterns. However, developing functional test patterns that attain satisfactory fault coverage is unacceptable for large scale designs due to the prohibitive development cost. Even if functional test patterns that can achieve high fault coverage are available, applying these test patterns at-speed for high speed chips requires very stringent timing accuracy, which can only be provided by very expensive automatic test equipments (ATEs).
The scan-based delay test approach where test patterns are generated by an automatic test pattern generator (ATPG) on designs that involve scan chains is increasingly used as a cost efficient alternative to the at-speed functional pattern approach to test large scale chips for performance-related failures [1, 14].
The transition delay fault model [18] is widely used in industry for its simplicity. Because of its similarity to the stuck-at fault model, ATPGs and fault simulators that are developed for stuck-at faults can be reused for transition delay faults with minor modifications. Unlike the path delay fault model [15] where the number of target faults is often exponential, the number of transition delay faults is linear to the number of circuit lines. This eliminates the need for critical path analysis and identification procedures, which are necessary for the path delay fault model.
Detection of a delay fault requires application of a two-pattern test; the first pattern that initializes the targeted faulty circuit line to a desired value and the second pattern that launches a transition at the circuit line and propagates the fault effect to one or more primary outputs or scan flip-flops. There are two different approaches to apply two-pattern tests in standard scan environment. In both approaches, the first pattern of a test pattern pair is scanned in through scan chains in the same fashion as a test pattern for a stuck-at fault is scanned in and the second pattern is derived from the first pattern.
In the first approach, referred to as skewed-load [12] or launch-by-shift, the second pattern is obtained by shifting in the first pattern by one more scan flip-flop. Hence, given a first pattern, there are only two possible patterns for the second pattern that differs only at the value for the first scan flip-flop whose scan input is connected to the scan chain input. This shift dependency restricts the number of combinations of test pattern pairs to 2n×2 [11] in standard scan environment, where n is the number of scan flip-flops in the scan chain.
In the second approach, referred to as broadside-load [12, 13] or launch-from-capture, the second pattern is obtained from the circuit response to the first pattern. Hence, the second pattern is given by the circuit response to the first pattern. Due to restriction to apply the second pattern in both approaches, transition delay fault coverage in standard scan environment is sometimes significantly lower than stuck-at fault coverage [12].
Several conventional techniques have been proposed to improve delay fault coverage in standard scan environment. In the techniques described in [6, 10], extra logic is inserted into the functional path to improve delay fault coverage in standard scan environment. A drawback of this method is performance degradation entailed due to additional logic that is inserted into the functional path. Enhanced scan testing [4] is a powerful scan technique that allows applying all possible 2n×(2n−1) combinations of pattern pairs to the circuit. Such faults that are not testable under standard scan environment but testable under full enhanced scan environment are referred to herein as dependency untestable faults. Since this technique requires to replace all standard scan cells by enhanced scan cells, which can hold two bits, the drawback of enhanced scan testing is high area overhead of enhanced scan cells.
In order to reduce area overhead, partial enhanced scan technique where only selected scan flip-flops are replaced by enhanced scan flip-flops is proposed by [2]. As a similar approach to the partial enhanced scan technique, in [12], dummy flip-flops are inserted to break shift dependency between selected pairs of adjacent scan flip-flops in the scan chain. In [9, 11], scan flip-flops are rearranged to minimize the number of pairs of adjacent scan flip-flops that drive same fanout cones. This reduces the number of transition delay faults that are untestable due to shift dependency between scan flip-flops. However, rearranging scan chains to enhance fault coverage may increase scan path routing overhead. Furthermore, for circuits where most state inputs are topologically correlated, satisfactory transition delay fault coverage may not be achieved in any order of scan flip-flops.
A simple example shows some problems with conventional approaches. FIG. 1 shows a circuit that has three state inputs, s1, s2, and s3, which are respectively driven by scan flip-flops D1, D2, and D3 during test application. Consider generating a test pattern pair V={V1, V2} for the slow-to-rise (STR) fault at line l that is to be applied to the circuit by using the conventional skewed-load approach. Initializing line l to a 0 requires assigning either s1 or s2 to a 0 at initialization test cycle T1. On the other hand, activating and propagating the STR fault at line l require assigning all state inputs s1, s2, and s3 to 1's at activation and propagation test cycle T2. However, if D1 (D2) is loaded with a 0 at time T1 to initialize line l, then the 0 at D1 (D2) shifts to D2 (D3) at the next cycle T2 and s2 (s3) is assigned a 0. This conflicts with the value 1, which is required at s2 (s3) to activate and propagate the fault effect. Hence, the STR fault at line l is untestable by the skewed-load approach in standard scan environment.
3. Definitions and Notations
Several definitions and notations are provided herein for a better understanding of this disclosure. It should be noted that these are only illustrative and should not be construed to limit the scope of the claimed invention. In this disclosure it is assumed that the sequential circuit under test (CUT), which has m primary inputs, p1, p2, . . . , pm, and n state inputs, s1, s2, . . . , sn, employs full scan and state input si, where i=1, 2, . . . , n, is driven by a corresponding scan flip-flop Di during test application. It is also assumed that all scan flip-flops in the CUT, D1, D2, . . . , Dn, where n is the number of scan flip-flops in the scan chain (state inputs), are connected to comprise one scan chain without loss of generality. The chain input of the scan chain is connected to the scan input of scan flip-flop D1 and the scan output of D1 is connected to the scan input of D2, and so on, and finally the scan output of Dn is connected to the scan chain output. It is further assumed that the scan path is constructed with only non-inverting outputs of scan flip-flops, which are also used to drive the functional path. Under the assumption, during scan shift cycles, the value loaded into scan flip-flop Di at time t is always the same as the value at the immediate predecessor of Di, i.e., Di−1 at the previous cycle time t−1. The above two assumptions are only for convenience of illustration and the disclosed techniques can be used for CUTs that have multiple scan chains and whose whole or part of scan paths are constructed by inverting outputs of scan flip-flops.
Let Vj={V1j, V2j} be a two pattern test (or test cube pair), which may be fully or partially specified, where V1j is the initialization pattern and V2j is the activation and propagation pattern of Vj. Each pattern Vjf, where f=1 or 2, consists of two parts: primary input part that is applied to primary inputs and scan input part that is applied to scan inputs.
The scan input part of initialization pattern Vj1 is applied to the CUT at initialization test cycle Tj1 via the scan chain and corresponding activation and propagation pattern Vj2 is applied the CUT at activation and propagation test cycle Tj2 by functional justification (when the broadside-load approach is used) or a shift operation (when the skewed-load approach is used).
If two pattern tests are applied via standard scan chains by using the skewed-load approach, all transition delay faults that require a 1 (0) at state input si−1 at the initialization test cycle and a 0 (1) at state input si at the activation and propagation test cycle to be detected are untestable even if they are testable in enhanced scan environment. Hence, a pair of values, the value assigned at si−1 in Vj1 and the value assigned at si in Vj2 are important to determine testability of transition delay faults when the skewed-load approach is used. We introduce dji to denote the pair of values, i.e., the value assigned at si−1 in Vj1 and the value assigned at si in Vj2. If two pattern test Vj is applied via a standard scan chain by using the skewed-load approach and Vj is fully specified, then dji is always 00 or 11.
Unlike state inputs, it is assumed that primary inputs are fully controllable, i.e., completely independent patterns can be applied to primary inputs at any two consecutive test cycles.